The Indian Institute of Technology (IIT) Guwahati researchers have developed methods to solve the problems in the computer systems domain. They have made fundamental contributions to memory architectures by preventing redundancy in data values and improving slow and frequently writes in multi-core processor systems.

They have contributed to the “multi-core processor-based systems that need an equally large on-chip memory to commensurate the data demands of the ever-growing applications and hence preventing energy consumption to ensure the temperature remains under the thermal design power (TDP) budget,” the IIT said.

IIT Guwahati researchers developed methods to evenly distribute the accesses across the overall memory capacity to reduce the wear-out pressure on heavily written locations and also worked in the area which avoids writing redundant values thus prolonging the wear-out.

The research is being led by Prof Hemangee K Kapoor, Department of Computer Science and Engineering (CSE), IIT Guwahati, and comprises a team of research scholars — Sukarn Agarwal, Palash Das, Sheel Sindhu Manohar, Arijit Nath, and Khushboo Rani.

“The application data access patterns are not uniformly distributed and hence leads to several orders of writes to certain memory locations compared to others. Such heavily written locations become prone to wear-out and thus prevents the use of complete memory device without error corrections,” explained Prof Kapoor.

“Slow and frequent writes can be re-directed to temporary SRAM partitions sparing the NVM from getting written with such frequent accesses. Such structures are called hybrid memories,” Prof Kapoor added.

The future challenges are to handle lifetime enhancement in presence of encryption methods used to secure the non-volatile memory and to handle temperature and process technology-driven disturbance errors introduced when the cells are read or written, Prof Kapoor said.

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